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8-channel EEG readout ASIC for Dry Electrodes
| Macro Name | 8-channel EEG readout ASIC for Dry Electrodes | |
| Type | Hard IP | |
| Short Description(max 128 characters) | "The 8-channel EEG readout ASIC is an ultra-low-power (ULP) solution for small size, autonomous, battery-powered wearable EEG acquisition systems with dry electrodes. " |
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| Extra description (optional) | The EEG system consists of nine active electrode (AE) ASICs and one back-end (BE) readout ASIC, enabling ambulatory EEG measurement by facilitating the use of dry electrodes and providing continuous-time monitoring of electrode-tissue impedance (ETI). The AE ASIC, that can be co-integrated on each electrode, has very high input impedance and low output impedance, which is ideal to supress cable motion artefact and power line interference while interfacing with dry electrodes. The BE ASIC consists of eight identical channels that receive analog outputs from the AEs, performing analog signal processing, i.e. extracts the EEG and real/imaginary components of the ETI signal, and 12 bit analog-to-digital conversion.The EEG channel has a programmable gain from 320 to 2200, and a programmable bandwidth of 69Hz to185Hz. The complete 8-channel system consumes less than 700μW power for all 24 signals including two built-in 12bit ADCs. A single channel consisting of two AE ASICs and the BE has 0.65μVrms (0.5-100 Hz) low input-referred noise over a wide range of ±500mV electrode offset. The system can also detect an electrode lead-off condition while maintaining the proper operation of other connected channels. | |
| Market category | Consumer Electronics, Industrial and medical | |
| Possible applications & standards | Wearable Healthcare and Lifestyle, Body Area Network, Complied to IEC60601-2-26 standard | |
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| Node / process | 0.18um 1P6M Mixed-Signal 1.8V/3.3V CMOS | |
| Foundry | TSMC | |
| Maturity | Silicon proven on prototypes, hence only white-box license (no corner characterization performed for high volume production) | |
| Leaflet or datasheet URL | ||
| Conference where this IP has been published | VLSI Circuits Symposium 2012 | |
| Paper publication URL | Download the paper here | |
| Chip area(for Hard IP only) (um**2) | AE (10440000) BE (33500000) | |
| Width (for Hard IP only) (um) | 3600 (AE chip), 5000 (BE chip) | |
| Height (for Hard IP only) (um) | 2900 (AE chip), 6700 (BE chip) | |
| Power (uW/MHz) | 1.15 uW/MHz | |
| Constant Power (mW) | 2.6 mW @ 2.2 GS/s | |
| Constant Leakage Power (uW) | 700uW | |
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