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ADC ( Analog Digital Converter ) 11 bit 250MS/s
This 250 MS/s 11 bit 1.7 mW two times interleaved fully dynamic pipelined SAR ADC in 40 nm CMOS is a good candidate for LTE-Advanced wireless receivers.
| Macro Name | ADC ( Analog Digital Converter ) 11 bit 250MS/s |
| Short Description(max 128 characters) | This 250 MS/s 11 bit 1.7 mW two times interleaved fully dynamic pipelined SAR ADC in 40 nm CMOS is a good candidate for LTE-Advanced wireless receivers. |
| Extra description (optional) | Imec offers a white-box IP license with support on a 250 MS/s 11 bit (9.5 ENOB) 1.7 mW two times interleaved fully dynamic pipelined SAR (Successive Approximation Register) ADC in 40 nm digital CMOS. This ADC achieves a peak SNDR of 62 dB, degrading to 56 dB at 250 MS/s and Nyquist frequency . This ADC is a good candidate for LTE-Advanced wireless receivers. |
| Market category | Communications - Data processing - Consumer Electronics |
| Possible applications & standards | This ADC is a good candidate for next generation Software Defined Radio ( SDR ) receivers, including LTE Advanced and the emerging generation of WIFI IEEE 802.11ac. |
| Primary Category | Analog & Mixed Signal IP:A2D Converter |
| Node / process | 40nm Low Power CMOS |
| Foundry | TSMC |
| Maturity | Silicon proven on prototypes, hence only white-box license (no corner characterization performed for high volume production) |
| Leaflet or datasheet URL | |
| Conference where this IP has been published | ISSCC2012 |
| Paper publication URL | Download the paper publication here |
| Chip area(for Hard IP only) (um**2) | 66300 |
| Width (for Hard IP only) (um) | 170 um |
| Height (for Hard IP only) (um) | 390 um ( 66000 um*2 is the core chip area ) |
| Power (uW/MHz) | 6.9 uW/MHz |
| Constant Power (mW) | 1.7 mW @ 250 MS/s |
| Constant Leakage Power (uW) | < 10 uW |
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