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/What we offer/Development/IP transfer/Analog & Mixed Signal IP: A2D Converter/ADC ( Analog Digital Converter )14bit 200MS/s

ADC ( Analog Digital Converter )14bit 200MS/s

This 200 MS/s 14 bit 2.3mW dynamic pipelined SAR ADC in 28nm CMOS with a new residue amplifier is suited for SDR receivers, eg LTE-A and IEEE 802.11ac.

Macro Name  ADC ( Analog Digital Converter )14bit 200MS/s
Short Description(max 128 characters)  This 200 MS/s 14 bit 2.3mW dynamic pipelined SAR ADC in 28nm CMOS with a new residue amplifier is suited for SDR receivers, eg LTE-A and IEEE 802.11ac.
Extra description (optional) Imec offers a white-box IP license with support on a low power 2x interleaved dynamic pipelined SAR ADC in 28nm digital CMOS, achieving a peak SNDR of 70.7 dB at 200 MS/s, at 2.3 mW consumption from a 0.9 V supply. This ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration.
Market category preselect from 6 possible choices, also allow for multiple selections (at the same time) : Communications - Data processing - Consumer Electronics - Automotive - Industrial and medical - Military /civil aerospace - all - other
Possible applications & standards This ADC is a good candidate for next generation Software Defined Radio ( SDR ) receivers, including LTE Advanced and the emerging generation of WIFI IEEE 802.11ac.
Primary Category  preselect from over 200 possible choices in sheet "IP Taxonomy", column A (e.g. Analog & Mixed Signal IP:A2D Converter)
Node / process 28 nm digital HPM CMOS
Foundry  TSMC
Maturity  Silicon proven on prototypes, hence only white-box license (no corner characterization performed for high volume production)
Leaflet or datasheet URL  
Conference where this IP has been published VLSI Circuits Symposium 2014
Paper publication URL Download the publication here
Chip area(for Hard IP only) (um**2) 350 000 including 1 nF reference decoupling capacitance
Width (for Hard IP only) (um) 700
Height (for Hard IP only) (um) 500
Power (uW/MHz) 11
Constant Power (mW) 2.3 mW at 200 MS/s
Constant Leakage Power (uW) 81
Features
  • 14 bit, 200 MS/s
  • ADC in 28nm digital CMOS
  • 72 dB Dynamic Range
  • Low noise peak SNDR of 70.7 dB at 200 MS/s, combined with a low power of 2.3 mW at 0.9V supply
  • Dynamically pipelined SAR (Successive Approximation Register)
  • New residue amplifier, and also interleaved channel time-constant calibration, both for lowering the noise at low power
  • Peak Schreier Figure-of-Merit (FOM) of 177.4 dB at 20 MS/s ; FOM of 170.6 dB at 200 MS/s
  • SNDR is higher than 70DB for the range of 40 - 200 MS/s ; SNDR is higher than 68 dB for 200 - 280 MS/s
  • Energy of 3.7 fJ per conversion step at 40 MS/s and low input frequency ; energy of 12.8 fJ per conversion step at 280 MS/s and at the Nyquist frequency
Deliverables
  • Option 1
  • Option 2
  • Option 3